Client:
Our client a leading Multinational Semiconductor Telecom Company requires Staff Digital Design Verification Engineer to based within its Sensor Team in Cork City, Ireland.
The role requires the candidates to be based onsite 5 days per week.
Role:
Working within the Sensors-based technology has a wide range of applications including navigation, gaming, smart user interface, multimedia, virtual reality, and augmented reality.
This challenging position offers the opportunity to work with leading edge sensor technologies embedded in smartphones, automotive, IOT, smartwatches as well as other consumer electronics device
Responsibilities:
- Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
- Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
- Verifying sensor algorithms RTL for ASIC tapeout quality delivery
- Test plan development based on Design documents and interaction with design/systems engineers
- Implementing C model integration within UVM framework.
- Writing SystemVerilog assertions
- Debugging, verifying, optimizing, and bit-exact matching with test vectors
- Analysing coverage data and working with Design teams to address coverage holes
- Develop/augment framework for running regressions
- Debugging regression failures with design/Systems teams
- Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level
- Python automation for improving workflows and team efficiency
- Participate in all project reviews
- Supporting software and other teams with debug
- Documentation
- Bachelor's degree in Science, Engineering, or related field.
Requirements & Experience:
- 6+ years ASIC design verification, UVM-based functional verification, or related work experience.
- Experience using formal verification tools like Jasper or VC_Formal is a plus
- Experience with SystemC and MATLAB are a plus.
- Gate level Simulation debug and usage of power extraction tools is a plus
- Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
- Experienced with Assertions like System Verilog Assertions
- Experience with debugging test failures and report verification result to achieve the expected code/functional/line coverage goals
- Extensive usage of RTL simulation tools.
- UVM, System Verilog, Perl/Python shell-scripting skills required
- Familiarity with C/C++
- Strong analytical skills and ability to work in a dynamic and fast paced team environment
- Excellent written and verbal skills
- Strong interpersonal skills and a good team player
Contact:
For further information please contact Mícheál at Software Placements Ltd on 00353 1 5254642 or email micheal@softwareplacements.ie