Client:

• Drive IC requirements definition.
• Develop and deliver System C model of the LO Chain / Chirp PLL
• Drive architecture selection and circuit / firmware implementation plan
• Actively contribute at a senior level to the generation of IC product specifications
• Direct, oversee and review circuit design and firmware activities.
• File patents for new technologies.
• Collaborate and lend your technical expertise to other teams including:
• Applications team to solve and anticipate customer issues.
• Reliability engineers to ensure that best practices for design robustness, ESD protection and reliability are followed at system level.
• Product Test engineers to define a cost optimised production test solution with the implementation of Design for Test circuits as applicable.
• Functional Safety engineers to agree a Safety Concept that can be implemented and verified.

Education:

• Masters/PhD desirable in electrical engineering, with a focus on semiconductor technology & microelectronics.(You will ideally be qualified to PhD level with industry experience in digitally assisted analog/RF signal chains on advanced CMOS)

• You will have 15+ years’ experience as system architect / circuit designer for highly integrated transceivers on advanced CMOS. System level  / behavioral modelling and simulation experience in Matlab, System C or similar. Requirements engineering
• Cooperation in spatially distributed teams with a good knowledge of analog and RF signal chains and digitally assisted analog/RF
• Design experience with circuits such as amplifiers, DACs, ADCs, PLLs, mixers, analog/digital filters and analog / digital control loops. Knowhow in PLL architectures is a plus.