Client:
Our client a leading a Multinational Semiconductor Organisation requires Lead, Staff and Senior FPGA Digital Design Engineer with background in PMIC for roles in Milan, Italy.
Role:
The group is seeking an experienced Lead, Staff and Senior FPGA Digital Design Engineers for there office in Milan to work on PMIC and hybrid mixed signal / power developments, for High-End / High-Volume electronic devices, such as Smartphones, Tablets and Consumer Accessories.
The Battery Consumer Power Milan Team is expanding its focus in Power Solutions, across a broad range of IC engineering profiles and levels of experience.
The candidates will be self-motivated, willing to learn exciting new technologies and develop new products, but also be able to work effectively within a talented group of individuals across multiple development locations.
- The candidates will join a team of Analog, Digital, Mixed-Signal CMOS designers, Mask Layout designers, Verification and Validation engineers, Algorithm and Software developers, Packaging and Test engineers, implementing PMIC state of the art technologies.
Responsibilities:
- FPGA development
- Synthesize RTL design to an FPGA platform
- Model analog function into the FPGA
- Power IP Development
- Execute based on IP Specification
- Improve Team Methodologies
- Power Management IC Development
- Execute on PMIC design, pre-silicon verification and post-silicon validation
- Provide support to physical design layout team
- Technical Customer Interface Engagement
- Participate in customer engagements, in support of technical feasibility
- IC development weekly meetings
Education:
- Master’s degree or higher in Electrical Engineering, Computer Science, or Computer Engineering
Experience:
At least 5 years of experience in:
- Basic FPGA simulation and development
- Basic IP Digital Design experience
- Good technical and analytical background with good problem-solving skills
- Great team worker with multi-discipline
- HDL programming languages (Verilog / SystemVerilog)
- Basic knowledge of Functional Oriented Verification
- Timing Constraints, Static Timing Analysis (STA), Gate Level Simulation (GLS)
- Good written and verbal communication
Nice to have:
- Xilinx Vivado development platform
- Scripting languages
- Analog Behavioral Models (SystemVerilog)
- Mixed-Signal Verification methodology
- UVM Verification (Universal Verification Methodology)
Contact:
For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie