LEAD/PRIN/SNR MIXED SIGNAL VERIFICATION-EDINBURGH-SCOTLAND

Location Edinburgh
Contact name: Micheal O’Maoldomhnaigh

Contact email: micheal@softwareplacements.ie
Job ref: 1134
Published: 3 months ago

 

Client:

Our client a leading Multinational Semiconductor Company requires a number of Lead/Principal/Senior Analog Mixed Signal Design Engineers for roles based in Edinburgh, Scotland. 


Role:



You will join a Power Team  who is primarily focused on PMIC and hybrid mixed-signal / power developments, for High-End / High-Volume electronic devices, such as Smartphones, Tablets and Consumer Accessories . The candidate will be self-motivated, willing to learn exciting new technologies and develop new products, but also be able to work effectively within a talented group of individuals.

Requirements:


The candidate will be involved in the following developments:
  • LDO, BUCK, BOOST, BUCK-BOOST, CHARGE-PUMP, SIMO (Single-Input / Multiple Outputs), IBB (Inverted BUCK-BOOST)
  • Power Sequencer, Oscillators, PLL, Bandgap, References, ADC, DAC, I/O, SPI, I2C, OTP, MTP, RAM, ROM, DFT
 
Responsibilities:
 
  • Human Resources Management
    • Build development teams, interview and recruit
o Mentor, provide technical leadership, enforce efficient techniques
o Support project management, task planning, schedule and resources
  • Verification IP Development
    • Improve Verification Team Flows, Methodologies and IP Golden-Models
    • Bridge Verification and Validation environments
  • Power Management IC Development
    • Drive PMIC pre-silicon verification and support PMIC post-silicon validation
    • Execute for 100% PMIC verification coverage, combining DMS and AMS, Top-Level and IP-Level
  • Technical Customer Interface Engagement
o IC Development Weekly meetings / IC Milestone Workshops
Education:
 
· Degree in Electrical Engineering, Computer Science, or Computer Engineering,

Experience:

You will have 5 + years of experience
  • Verification Team Leading/AMS Verification experience
  • Strong technical and analytical background with good problem-solving skills
  • Strong team worker with multi-discipline, multi-cultural and multi-site environments
  • HDL programming languages (Verilog / SystemVerilog)
  • IC Top-Level Digital UVM Verification (Universal Verification Methodology)
  • Functional Oriented and Randomized Verification, Gate Level Simulation (GLS)
  • Regressions and Coverage
  • Analog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet)
  • Excellent written and verbal communication
 
Preferred Qualifications:
  • Verification experience with multiple products introduced into the market, with Integrated Power functions
  • Verification Planning tools (ePlanner, vManager)
  • Top-Level IC UVM Environment Setup, Formal Based Verification, Emulation
  • Property Specification Language (PSL), SystemVerilog Assertions (SVA)
  • Good understanding of Mixed-Signal Design Flow and Top-Down development methodology
  • Mixed-Signal Verification methodology and tools (AMS / APS / Flex)
  • Proficient with Cadence Suite (Virtuoso IUS)
  • Scripting languages (Shell, TCL, PERL, Python) for bench automation
  • Lab silicon bring-up and Production Test support experiences
  • Experience with Multiple Power and Clock domains
Contact:

For further information please contact Mícheál at Software Placements on 00353 1 525464 or email micheal@softwareplacements.ie