Contact name: Micheal O’Maoldomhnaigh

Contact email:
Job ref: 1200
Published: 11 months ago



Our client a leading Multinational Semiconductor Power Company requires Senior Analog Mixed Signal Design Engineer for position based in Catania, Italy.




The Team is expanding its focus in Power Solutions, across a broad range of IC engineering profiles and levels of experience, including Analog Designer, Digital Designer, Mixed-Signal Designer, Verification Engineer, Silicon Evaluation Engineer and Layout Designer.


The candidate will be involved in the following developments, from definition to production:


  • LDO, BUCK, BOOST, BUCK-BOOST, CHARGE-PUMP, SIMO (Single-Input / Multiple Outputs)
  • IBB (Inverted BUCK-BOOST), ICP (Inverted CHARGE-PUMP), Negative LDO
  • Power Sequencer, Oscillators, PLL, Bandgap, References, ADC, DAC, I/O, SPI, I2C, SPMI, OTP, MTP, RAM, ROM, DFT




  • Mixed-Signal Verification IP Development
  • Improve AMS Verification Team Flows & Methodologies
  • Bridge AMS / DMS Verification and Bench Evaluation environments
  • Power Management IC Development
  • Integrate IPs, improve Integration Flows & Methodologies
  • Execute on PMIC pre-silicon AMS verification and support PMIC post-silicon bench evaluation
  • Execute for 100% PMIC verification coverage, combining DMS and AMS, Top-Level and IP-Level
  • Technical Customer Interface Engagement
  • Participate in customer engagements, in support of technical feasibility and proposals
  • IC Milestone Workshops
  • Human Resources Management
  • Provide Mentorship and technical leadership, setting up framework and structure for efficient development flows
  • Enable a culture of continuous learning and improvement
  • Support project management and task planning



  • Degree in Electrical Engineering, Computer Science, or Computer Engineering
  • You will have 5+ years of experience IC AMS Verification Leading experience with multiple products introduced into the market
  • Mixed-Signal Verification methodology and tools (AMS / APS / Flex)
  • Good understanding of Mixed-Signal Design Flow and Top-Down development methodology
  • Great technical and analytical background with good problem-solving skills
  • Great team worker with multi-discipline, multi-cultural and multi-site environments
  • Analog Functional and Parametric Verification
  • Process - Voltage - Temperature (PVT) Corners, Layout Parameter Extraction (LPE) Simulations
  • Analog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet)
  • Good written and verbal communication



Preferred Qualifications & Experience:



  • Proficient with Cadence Suite (Virtuoso ADE Spectre)
  • Scripting languages (Shell, TCL, PERL, Python)
  • HDL programming languages (Verilog / SystemVerilog)
  • Good understanding of Power IP Topologies
  • Experience with Multiple Power and Clock domains
  • IC Top-Level Digital UVM Environment Setup & Verification (Universal Verification Methodology)
  • Verification Planning tools (ePlanner, vManager)
  • Functional Oriented and Randomized Verification, Gate Level Simulation (GLS)
  • Property Specification Language (PSL), SystemVerilog Assertions (SVA)
  • Regressions and Coverage
  • Lab silicon bring-up evaluation and Production Test support experiences





For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email