Client:
Our client a leading Multinational Semiconductor EDA provider requires Lead Physical Design Engineer for role based in Cork City, Ireland.
Role:
In this team you will develop methodology and implementation flows that can achieve the best possible PPA (Performance, Power and Area) for these processor IP.
Responsibilities:
- Develop and maintain flows and scripts for the physical implementation.
- Debug and optimize the flow for performance-oriented and power-oriented IP cores in advanced process nodes, such as 16nm/7nm/5nm.
- Manage the regression infrastructure that tracks the quality of the RTL/flow development as well as the PPA of the key designs.
- Participate in benchmarking PPAs for customer engagements.
Educational:
- MS in Electrical Engineering or Computer Science
Requirements:
- Strong understanding of digital logic design, processor design, and computer architecture is desirable.
- Must have excellent knowledge of ASIC design flows and issues. Prior working experience on any Cadence physical implementation tool is a plus.
- A good working knowledge on Perl is required. Experience on any other programming language is a plus.
- Must be an excellent team player in a fast-paced environment.
Contact:
For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie